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SAFECOMP
2000
Springer
15 years 7 months ago
Speeding-Up Fault Injection Campaigns in VHDL Models
Abstract. Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents ...
B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reo...
EWC
2010
91views more  EWC 2010»
15 years 2 months ago
Multiobjective global surrogate modeling, dealing with the 5-percent problem
When dealing with computationally expensive simulation codes or process measurement data, surrogate modeling methods are firmly established as facilitators for design space explor...
Dirk Gorissen, Ivo Couckuyt, Eric Laermans, Tom Dh...
CASES
2006
ACM
15 years 10 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 4 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
CODES
2004
IEEE
15 years 7 months ago
RTOS-centric hardware/software cosimulator for embedded system design
This paper presents an RTOS-centric hardwareisoftware cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is tha...
Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiy...