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127
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PATMOS
2005
Springer
15 years 10 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
138
Voted
PATMOS
2004
Springer
15 years 10 months ago
Optimal Logarithmic Representation in Terms of SNR Behavior
This paper investigates the Signal-to-Noise Ratio (SNR) performance of the Logarithmic Number System (LNS) representation against the SNR performance of the fixed-point representa...
Panagiotis D. Vouzis, Vassilis Paliouras
RTSS
1996
IEEE
15 years 9 months ago
Commit processing in distributed real-time database systems
W e investigate here the performance implications of supporting transaction atomicity in a distributed realtime database system. Using a detailed simulation model of a firm-deadli...
Ramesh Gupta, Jayant R. Haritsa, Krithi Ramamritha...
CCS
2008
ACM
15 years 7 months ago
A general model of probabilistic packet marking for IP traceback
In this paper, we model Probabilistic Packet Marking (PPM) schemes for IP traceback as an identification problem of a large number of markers. Each potential marker is associated ...
Liming Lu, Mun Choon Chan, Ee-Chien Chang
IWCMC
2006
ACM
15 years 11 months ago
Modeling key agreement in multi-hop ad hoc networks
Securing multicast communications in ad hoc networks has become one of the most challenging research directions in the areas of wireless networking and security. This is especiall...
Giovanni Di Crescenzo, Maria Striki, John S. Baras