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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 23 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ICPADS
2005
IEEE
15 years 12 months ago
A Two-Level Strategy for Topology Control in Wireless Sensor Networks
— This paper presents a two-level strategy for topology control in wireless sensor networks. The energy saving methods in most of the existing research work can be categorized in...
Bolian Yin, Hongchi Shi, Yi Shang
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
15 years 11 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
IWANN
2001
Springer
15 years 10 months ago
Is Neural Network a Reliable Forecaster on Earth? A MARS Query!
: Long-term rainfall prediction is a challenging task especially in the modern world where we are facing the major environmental problem of global warming. In general, climate and ...
Ajith Abraham, Dan Steinberg
199
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ICPP
1997
IEEE
15 years 10 months ago
The Affinity Entry Consistency Protocol
In this paper we propose a novel software-only distributed sharedmemory system (SW-DSM), the Affinity Entry Consistency (AEC) protocol. The protocol is based on Entry Consistency ...
Cristiana Bentes Seidel, Ricardo Bianchini, Claudi...