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JPDC
2000
141views more  JPDC 2000»
15 years 3 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
HPCA
2006
IEEE
16 years 3 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
OTM
2009
Springer
15 years 10 months ago
A Component Assignment Framework for Improved Capacity and Assured Performance in Web Portals
Abstract. Web portals hosting large-scale internet applications have become popular due to the variety of services they provide to their users. These portals are developed using co...
Nilabja Roy, Yuan Xue, Aniruddha S. Gokhale, Larry...
120
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IPPS
1998
IEEE
15 years 7 months ago
Hiding Communication Latency in Data Parallel Applications
Interprocessor communication times can be a significant fraction of the overall execution time required for data parallel applications. Large communication to computation ratios o...
Vivek Garg, David E. Schimmel
120
Voted
RECONFIG
2009
IEEE
165views VLSI» more  RECONFIG 2009»
15 years 10 months ago
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
Muhammad Aqeel Wahlah, Kees G. W. Goossens