439 search results - page 30 / 88 » Performance Modeling of MANET Interconnectivity |
105
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PE
2006
Springer
14 years 9 months ago
2006
Springer
In a multi-level cache such as those used for web caching, a hit at level l leads to the caching of the requested object in all intermediate caches on the reverse path (levels l -...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
72
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ISCA
2007
IEEE
15 years 3 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
FPL
2008
Springer
14 years 11 months ago
2008
Springer
A Customized Reconfigurable Interconnection Network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirem...
CNSR
2006
IEEE
15 years 3 months ago
2006
IEEE
The deployment of Reconfigurable Optical Add/Drop Multiplexers (ROADMs) is going to change the conventional architecture for metro networks. In this paper, we present detailed fea...