439 search results - page 31 / 88 » Performance Modeling of MANET Interconnectivity |
69
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ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
103
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HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
Communication-based design represents a formal approach to systemon-a-chip design that considers communication between components as important as the computations they perform. Ou...
ISCA
2008
IEEE
15 years 3 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Existing Full-wave Model Order Reduction (FMOR) approaches are based on Expanded Taylor Series Approximations (ETAS) of the oscillatory full-wave system matrix. The accuracy of su...