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» Performance Modeling of MANET Interconnectivity
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DATE
2004
IEEE
157views Hardware» more  DATE 2004»
15 years 3 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
DATE
2009
IEEE
147views Hardware» more  DATE 2009»
15 years 6 months ago
Decoupling capacitor planning with analytical delay model on RLC power grid
— Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltag...
Ye Tao, Sung Kyu Lim
ERSA
2009
146views Hardware» more  ERSA 2009»
14 years 9 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
ICRA
2008
IEEE
136views Robotics» more  ICRA 2008»
15 years 6 months ago
Toward a multi-disciplinary model for bio-robotic systems
Abstract— The design of robotic systems involves contributions from several areas of science and engineering. Electrical, mechanical and software components must be integrated to...
Richard Primerano, David Wilkie, William Regli
SLIP
2005
ACM
15 years 5 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...