439 search results - page 52 / 88 » Performance Modeling of MANET Interconnectivity |
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
DAC
1999
ACM
16 years 24 days ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
DAC
2002
ACM
16 years 24 days ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
104
click to vote
CASCON
1996
15 years 1 months ago
1996
Because changes to the database (DB) and workload occur during a DB system's lifetime, the physical DB design must evolve to sustain good performance. These changes are carri...
IEEEHPCS
2010
14 years 10 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...