439 search results - page 57 / 88 » Performance Modeling of MANET Interconnectivity |
111
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ISQED
2007
IEEE
15 years 6 months ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
103
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MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
WSC
1997
15 years 1 months ago
1997
Components of modern parallel systems are becoming quite complex with many features and variations. An integrated modeling of these components (interconnection network, messaging ...
RECONFIG
2009
IEEE
15 years 6 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
SCI
1999
Springer
15 years 4 months ago
1999
Springer
This paper describes the parallelization of a commercial molecular dynamics simulation code, GROMOS96, on a SCI (Scalable Coherent Interface) interconnected PC cluster. The underly...