Sciweavers

6709 search results - page 116 / 1342
» Performance Modelling of the Computational Hardware: A Stati...
Sort
View
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
16 years 1 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
WSC
2000
15 years 2 months ago
New results on procedures that select the best system using CRN
One use of simulation is to inform decision makers that seek to select the best of several alternative systems. The system with the highest (or lowest) mean value for simulation o...
Stephen E. Chick, Koichiro Inoue
TOG
2002
112views more  TOG 2002»
15 years 10 days ago
Ray tracing on programmable graphics hardware
Recently a breakthrough has occurred in graphics hardware: fixed function pipelines have been replaced with programmable vertex and fragment processors. In the near future, the gr...
Timothy J. Purcell, Ian Buck, William R. Mark, Pat...
113
Voted
FPT
2005
IEEE
142views Hardware» more  FPT 2005»
15 years 6 months ago
Custom Hardware Architectures for Posture Analysis
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
M. P. T. Juvonen, José Gabriel F. Coutinho,...
91
Voted
FPL
2005
Springer
115views Hardware» more  FPL 2005»
15 years 6 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...