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» Performance Modelling of the Computational Hardware: A Stati...
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86
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MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
15 years 7 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
ECCV
2000
Springer
16 years 2 months ago
Model-Based Initialisation for Segmentation
The initialisation of segmentation methods aiming at the localisation of biological structures in medical imagery is frequently regarded as a given precondition. In practice, howev...
Christian Brechbühler, Gábor Szé...
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
15 years 6 months ago
Formal performance analysis and simulation of UML/SysML models for ESL design
UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative perfo...
Alexander Viehl, Timo Schönwald, Oliver Bring...
85
Voted
EUROPAR
2008
Springer
15 years 2 months ago
Mapping Heterogeneous Distributed Applications on Clusters
Performance of distributed applications largely depends on the mapping of their components on the underlying architecture. On one mponent-based approaches provide an abstraction su...
Sylvain Jubertie, Emmanuel Melin, Jér&eacut...
86
Voted
VLSID
2005
IEEE
129views VLSI» more  VLSID 2005»
16 years 1 months ago
A RISC Hardware Platform for Low Power Java
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
Paul Capewell, Ian Watson