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» Performance Modelling of the Computational Hardware: A Stati...
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146
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IEEEPACT
2009
IEEE
14 years 10 months ago
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
HPCA
1997
IEEE
15 years 5 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...
166
Voted
BMCBI
2005
169views more  BMCBI 2005»
15 years 21 days ago
Genetic interaction motif finding by expectation maximization - a novel statistical model for inferring gene modules from synthe
Background: Synthetic lethality experiments identify pairs of genes with complementary function. More direct functional associations (for example greater probability of membership...
Yan Qi 0003, Ping Ye, Joel S. Bader
DRM
2005
Springer
15 years 6 months ago
Statistical audio watermarking algorithm based on perceptual analysis
In this paper, we describe a novel statistical audio watermarking scheme. Under the control of the masking thresholds, watermark is embedded adaptively and transparently in the pe...
Xiaomei Quan, Hongbin Zhang
117
Voted
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 6 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf