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» Performance Modelling of the Computational Hardware: A Stati...
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120
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ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
15 years 4 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
102
Voted
NAACL
2010
14 years 10 months ago
The Best Lexical Metric for Phrase-Based Statistical MT System Optimization
Translation systems are generally trained to optimize BLEU, but many alternative metrics are available. We explore how optimizing toward various automatic evaluation metrics (BLEU...
Daniel Cer, Christopher D. Manning, Daniel Jurafsk...
91
Voted
ISMVL
2005
IEEE
108views Hardware» more  ISMVL 2005»
15 years 6 months ago
Approaching the Physical Limits of Computing
As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. H...
Michael P. Frank
103
Voted
CVPR
1998
IEEE
16 years 2 months ago
Background Modeling for Segmentation of Video-Rate Stereo Sequences
Stereo sequences promise to be a powerful method for segmenting images for applications such as tracking human figures. We present a method of statistical background modeling for ...
Christopher K. Eveland, Kurt Konolige, Robert C. B...
110
Voted
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
15 years 6 months ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...