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JPDC
2000
141views more  JPDC 2000»
15 years 1 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
IPPS
2010
IEEE
14 years 11 months ago
Improving numerical reproducibility and stability in large-scale numerical simulations on GPUs
The advent of general purpose graphics processing units (GPGPU's) brings about a whole new platform for running numerically intensive applications at high speeds. Their multi-...
Michela Taufer, Omar Padron, Philip Saponaro, Sand...
IEEEPACT
2002
IEEE
15 years 6 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
IPPS
1997
IEEE
15 years 5 months ago
An Architecture Workbench for Multicomputers
The large design space of modern computer architectures calls for performance modelling tools to facilitate the evaluation of different alternatives. In this paper, we give an ove...
Andy D. Pimentel, Louis O. Hertzberger
SAMOS
2009
Springer
15 years 8 months ago
Prediction in Dynamic SDRAM Controller Policies
Abstract. Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution ti...
Ying Xu, Aabhas S. Agarwal, Brian T. Davis