Sciweavers

2964 search results - page 385 / 593
» Performance Prediction of a Parallel Simulator
Sort
View
123
Voted
HPCA
2004
IEEE
16 years 5 months ago
Hardware Support for Prescient Instruction Prefetch
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wan...
134
Voted
ICCS
2009
Springer
15 years 11 months ago
GPU Accelerated RNA Folding Algorithm
Many bioinformatics studies require the analysis of RNA or DNA structures. More specifically, extensive work is done to elaborate efficient algorithms able to predict the 2-D fold...
Guillaume Rizk, Dominique Lavenier
147
Voted
CCGRID
2008
IEEE
15 years 11 months ago
A Proactive Non-Cooperative Game-Theoretic Framework for Data Replication in Data Grids
— Data grids and its cost effective nature has taken on a new level of interest in recent years; amalgamation of different providers results in increased capacity as well as lowe...
Ali Elghirani, Riky Subrata, Albert Y. Zomaya
151
Voted
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
15 years 11 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
128
Voted
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
15 years 10 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...