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152
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CODES
2006
IEEE
15 years 10 months ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
138
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SC
2005
ACM
15 years 10 months ago
2005
ACM
The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end computing (HEC) platforms, primarily because of their generality, ...
113
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IEEEPACT
2009
IEEE
15 years 11 months ago
2009
IEEE
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
162
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HPCA
2011
IEEE
14 years 8 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
146
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DAC
2008
ACM
16 years 5 months ago
2008
ACM
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...