2964 search results - page 451 / 593 » Performance Prediction of a Parallel Simulator |
136
click to vote
GLOBECOM
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— This paper presents an Interleaver-Division Multiple Access (IDMA) based architecture with single-user decoding using parallel concatenated non-linear trellis codes (PC...
133
click to vote
IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
139
click to vote
IEEEPACT
2005
IEEE
15 years 10 months ago
2005
IEEE
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
160
click to vote
GRID
2005
Springer
15 years 10 months ago
2005
Springer
— We present the ASKALON environment whose goal is to simplify the development and execution of workflow applications on the Grid. ASKALON is centered around a set of high-level...
119
click to vote
ISSS
2002
IEEE
15 years 9 months ago
2002
IEEE
In this paper, we introduce a Round–robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of b...