2964 search results - page 514 / 593 » Performance Prediction of a Parallel Simulator |
126
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ISCA
1997
IEEE
15 years 7 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
136
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ISCA
1994
IEEE
15 years 7 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
121
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ANCS
2007
ACM
15 years 7 months ago
2007
ACM
We propose a distributed congestion management scheme for non-blocking, 3-stage Clos networks, comprising plain buffered crossbar switches. VOQ requests are routed using multipath...
113
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ASPDAC
2005
ACM
15 years 5 months ago
2005
ACM
Abstract— A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component...
140
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CODES
2008
IEEE
15 years 5 months ago
2008
IEEE
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...