2964 search results - page 519 / 593 » Performance Prediction of a Parallel Simulator |
164
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ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
164
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ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
CODES
2008
IEEE
15 years 4 months ago
2008
IEEE
To provide Quality of Service (QoS) guarantees in open and unpredictable environments, the utilization control problem is defined to keep the processor utilization at the schedula...
126
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SIGCOMM
2005
ACM
15 years 3 months ago
2005
ACM
Hash table is used as one of the fundamental modules in several network processing algorithms and applications such as route lookup, packet classification, per-flow state manage...