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DSD
2002
IEEE
90views Hardware» more  DSD 2002»
15 years 2 months ago
Simplifying Instruction Issue Logic in Superscalar Processors
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
Toshinori Sato, Itsujiro Arita
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
15 years 2 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
VISUALIZATION
1999
IEEE
15 years 2 months ago
A Multi-Threaded Streaming Pipeline Architecture for Large Structured Data Sets
Computer simulation and digital measuring systems are now generating data of unprecedented size. The size of data is becoming so large that conventional visualization tools are in...
C. Charles Law, Ken Martin, William J. Schroeder, ...
ASPLOS
1998
ACM
15 years 2 months ago
Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units
This paper proposes a technique that enables performing multi-cycle (multiplication, division, square-root ...) computations in a single cycle. The technique is based on the notio...
Daniel Citron, Dror G. Feitelson, Larry Rudolph
CEC
2009
IEEE
15 years 1 months ago
JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
Olivier Brousse, Jérémie Guillot, Th...