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» Performance Prediction of a Parallel Simulator
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IPPS
2010
IEEE
14 years 11 months ago
Improving the performance of hypervisor-based fault tolerance
Hypervisor-based fault tolerance (HBFT), a checkpoint-recovery mechanism, is an emerging approach to sustaining mission-critical applications. Based on virtualization technology, H...
Jun Zhu, Wei Dong, Zhefu Jiang, Xiaogang Shi, Zhen...
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IPPS
2006
IEEE
15 years 7 months ago
A performance model for fine-grain accesses in UPC
UPC’s implicit communication and fine-grain programming style make application performance modeling a challenging task. The correspondence between remote references and communi...
Zhang Zhang, S. R. Seidel
ICDCS
2006
IEEE
15 years 7 months ago
A Locality-Aware Cooperative Cache Management Protocol to Improve Network File System Performance
In a distributed environment the utilization of file buffer caches in different clients may vary greatly. Cooperative caching is used to increase cache utilization by coordinatin...
Song Jiang, Fabrizio Petrini, Xiaoning Ding, Xiaod...
CSREAESA
2003
15 years 2 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ISPASS
2009
IEEE
15 years 8 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...