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» Performance Studies of a Parallel Prolog Architecture
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DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 3 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
ASPLOS
2009
ACM
15 years 5 months ago
Performance analysis of accelerated image registration using GPGPU
This paper presents a performance analysis of an accelerated 2-D rigid image registration implementation that employs the Compute Unified Device Architecture (CUDA) programming e...
Peter Bui, Jay B. Brockman
CCGRID
2006
IEEE
15 years 4 months ago
Evaluating Performance and Scalability of Advanced Accelerator Simulations
Advanced accelerator simulations have played a prominent role in the design and analysis of modern accelerators. Given that accelerator simulations are computational intensive and...
Jungmin Lee, Zhiling Lan, J. Amundson, P. Spentzou...
CIC
2003
150views Communications» more  CIC 2003»
14 years 12 months ago
Performance Modeling of a Cluster of Workstations
Using off-the-shelf commodity workstations to build a cluster for parallel computing has become a common practice. In studying or designing a cluster of workstations one should ha...
Ahmed M. Mohamed, Lester Lipsky, Reda A. Ammar
ASPLOS
1992
ACM
15 years 2 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam