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» Performance Studies of a Parallel Prolog Architecture
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PPOPP
2012
ACM
13 years 6 months ago
Better speedups using simpler parallel programming for graph connectivity and biconnectivity
Speedups demonstrated for finding the biconnected components of a graph: 9x to 33x on the Explicit Multi-Threading (XMT) many-core computing platform relative to the best serial ...
James A. Edwards, Uzi Vishkin
DATE
2005
IEEE
113views Hardware» more  DATE 2005»
15 years 4 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
IPPS
2003
IEEE
15 years 3 months ago
Cost/Performance Tradeoffs in Network Interconnects for Clusters of Commodity PCs
The definition of a commodity component is quite obvious when it comes to the PC as a basic compute engine and building block for clusters of PCs. Looking at the options for a mo...
Christian Kurmann, Felix Rauch, Thomas Stricker
HPCA
2000
IEEE
15 years 3 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
DAC
2002
ACM
15 years 11 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik