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» Performance Studies of a Parallel Prolog Architecture
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IFIP
2004
Springer
15 years 4 months ago
The Inherent Queuing Delay of Parallel Packet Switches
The parallel packet switch (PPS) extends the inverse multiplexing architecture, and is extensively used as the core of contemporary commercial switches. A key factor in the perfor...
Hagit Attiya, David Hay
CLUSTER
2002
IEEE
14 years 10 months ago
ZENTURIO: An Experiment Management System for Cluster and Grid Computing
The need to conduct and manage large sets of experiments for scientific applications dramatically increased over the last decade. However, there is still very little tool support ...
Radu Prodan, Thomas Fahringer
ISPASS
2010
IEEE
15 years 5 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
HPCA
2003
IEEE
15 years 11 months ago
Hierarchical Backoff Locks for Nonuniform Communication Architectures
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...
Zoran Radovic, Erik Hagersten
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 2 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...