372 search results - page 42 / 75 » Performance Studies of a Parallel Prolog Architecture |
ASAP
2008
IEEE
15 years 5 months ago
2008
IEEE
Cooperative MIMO is a new technique that allows disjoint wireless communication nodes (e.g. wireless sensors) to form a virtual antenna array to increase bandwidth, reliability an...
IEEEPACT
2008
IEEE
15 years 5 months ago
2008
IEEE
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
HPCA
2009
IEEE
15 years 11 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
JPDC
2007
14 years 10 months ago
2007
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...
HPCA
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...