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» Performance Study of a Concurrent Multithreaded Processor
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CONCURRENCY
2006
140views more  CONCURRENCY 2006»
14 years 9 months ago
An efficient memory operations optimization technique for vector loops on Itanium 2 processors
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
ISPASS
2009
IEEE
15 years 4 months ago
Analyzing CUDA workloads using a detailed GPU simulator
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...
Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, He...
ICSE
2010
IEEE-ACM
15 years 2 months ago
Falcon: fault localization in concurrent programs
Concurrency fault are difficult to find because they usually occur under specific thread interleavings. Fault-detection tools in this area find data-access patterns among threa...
Sangmin Park, Richard W. Vuduc, Mary Jean Harrold
IEEEPACT
2006
IEEE
15 years 3 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
65
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IPPS
2008
IEEE
15 years 3 months ago
Balancing HPC applications through smart allocation of resources in MT processors
Abstract—Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1...
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazor...