155 search results - page 28 / 31 » Performance Study of a Concurrent Multithreaded Processor |
ETS
2010
IEEE
15 years 18 days ago
2010
IEEE
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...
103
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HPCA
2002
IEEE
15 years 4 months ago
2002
IEEE
Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configura...
HPCA
2009
IEEE
16 years 1 days ago
2009
IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
101
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SIGARCH
2008
14 years 11 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
187
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CODES
2011
IEEE
13 years 11 months ago
2011
IEEE
The trend towards many-core systems comes with various issues, among them their highly dynamic and non-predictable workloads. Hence, new paradigms for managing resources of many-c...