The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Accurate and systematic channel simulation technique is critical for performance verification of digital transceiver design over wireless channels. Despite the abundant results on ...
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rain...