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HPCA
2012
IEEE
13 years 5 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
15 years 4 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
CODES
2008
IEEE
15 years 4 months ago
Online adaptive utilization control for real-time embedded multiprocessor systems
To provide Quality of Service (QoS) guarantees in open and unpredictable environments, the utilization control problem is defined to keep the processor utilization at the schedula...
Jianguo Yao, Xue Liu, Mingxuan Yuan, Zonghua Gu
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
15 years 4 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
ICS
2007
Tsinghua U.
15 years 4 months ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi