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HIPC
2004
Springer
15 years 3 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
IEEEPACT
2006
IEEE
15 years 3 months ago
Fast, automatic, procedure-level performance tuning
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
Zhelong Pan, Rudolf Eigenmann
IPPS
2006
IEEE
15 years 3 months ago
Parallelization of module network structure learning and performance tuning on SMP
As an extension of Bayesian network, module network is an appropriate model for inferring causal network of a mass of variables from insufficient evidences. However learning such ...
Hongshan Jiang, Chunrong Lai, Wenguang Chen, Yuron...
CIKM
2008
Springer
14 years 12 months ago
Modeling LSH for performance tuning
Although Locality-Sensitive Hashing (LSH) is a promising approach to similarity search in high-dimensional spaces, it has not been considered practical partly because its search q...
Wei Dong, Zhe Wang, William Josephson, Moses Chari...
ICASSP
2007
IEEE
14 years 11 months ago
SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding
This paper presents a set of fast algorithm and VLSI architecture for HDTV-sized H.264 fractional motion estimation. To solve the long computational latency in HD-sized applicatio...
Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang