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» Performance analysis and optimization of latency insensitive...
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79
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DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 2 months ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule...
ISCAS
2007
IEEE
113views Hardware» more  ISCAS 2007»
15 years 4 months ago
A General Noncoherent Chaos-Shift-Keying Communication System and its Performance Analysis
— A general noncoherent chaos-shift-keying (CSK) communication system with adjustable weights is proposed in this paper. The performance of the system under additive white Gaussi...
Hongbin Chen, Jiuchao Feng, Chi K. Michael Tse
HPCA
2007
IEEE
15 years 10 months ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
PLDI
1995
ACM
15 years 1 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
71
Voted
ICCAD
1998
IEEE
107views Hardware» more  ICCAD 1998»
15 years 1 months ago
Techniques for energy minimization of communication pipelines
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
Gang Qu, Miodrag Potkonjak