Sciweavers

1370 search results - page 64 / 274
» Performance analysis and optimization of latency insensitive...
Sort
View
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
15 years 3 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 2 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
DEDS
2010
157views more  DEDS 2010»
14 years 7 months ago
On-line Optimal Control of a Class of Discrete Event Systems with Real-Time Constraints
We consider Discrete Event Systems (DES) involving tasks with real-time constraints and seek to control processing times so as to minimize a cost function subject to each task mee...
Jianfeng Mao, Christos G. Cassandras
EIT
2008
IEEE
14 years 11 months ago
Design and analysis of efficient reconfigurable wavelet filters
Abstract--Real-time image and multimedia processing applications such as video surveillance and telemedicine can have dynamic requirements of system latency, throughput, and power ...
Amit Pande, Joseph Zambreno
ECRTS
2006
IEEE
15 years 3 months ago
Optimal deadline assignment for periodic real-time tasks in dynamic priority systems
Real-time systems are often designed using a set of periodic tasks. Task periods are usually set by the system requirements, but deadlines and computation times can be modified i...
Patricia Balbastre, Ismael Ripoll, Alfons Crespo