Sciweavers

1370 search results - page 75 / 274
» Performance analysis and optimization of latency insensitive...
Sort
View
JUCS
2000
120views more  JUCS 2000»
14 years 9 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
BMCBI
2008
97views more  BMCBI 2008»
14 years 10 months ago
Quantitative analysis of numerical solvers for oscillatory biomolecular system models
Background: This article provides guidelines for selecting optimal numerical solvers for biomolecular system models. Because various parameters of the same system could have drast...
Chang F. Quo, May D. Wang
WSC
2004
14 years 11 months ago
Capacity Analysis of Automated Material Handling Systems in Semiconductor Fabs
A critical aspect of semiconductor manufacturing is the design and analysis of material handling and production control polices to optimize fab performance. As wafer sizes have in...
Michael E. Kuhl, Julie Christopher
SIGSOFT
2007
ACM
15 years 10 months ago
A framework for characterization and analysis of software system scalability
The term scalability appears frequently in computing literature, but it is a term that is poorly defined and poorly understood. The lack of a clear, consistent and systematic trea...
Leticia Duboc, David S. Rosenblum, Tony Wicks
IISWC
2008
IEEE
15 years 4 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood