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» Performance analysis of distributed embedded systems
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RTAS
2008
IEEE
15 years 10 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
ISPASS
2005
IEEE
15 years 9 months ago
Analysis of Network Processing Workloads
Abstract— Network processing is becoming an increasingly important paradigm as the Internet moves towards an architecture with more complex functionality inside the network. Mode...
Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
131
Voted
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
15 years 8 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 10 months ago
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-onchips (SOCs). To increase the utilization of memory redundancy, the BISR t...
Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
ECRTS
2007
IEEE
15 years 10 months ago
Predictable Paging in Real-Time Systems: A Compiler Approach
Conventionally, the use of virtual memory in real-time systems has been avoided, the main reason being the difficulties it provides to timing analysis. However, there is a trend ...
Isabelle Puaut, Damien Hardy