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DAC
1998
ACM
16 years 7 months ago
Approximation and Decomposition of Binary Decision Diagrams
Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and mode...
Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple...
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
16 years 10 days ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...
GLVLSI
2008
IEEE
147views VLSI» more  GLVLSI 2008»
16 years 23 days ago
Statistical timing analysis of flip-flops considering codependent setup and hold times
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Safar Hatami, Hamed Abrishami, Massoud Pedram
PEWASUN
2006
ACM
16 years 7 days ago
Experimental analysis of a transport protocol for ad hoc networks (TPA)
Many previous papers have pointed out that TCP performance in multi-hop ad hoc networks is not optimal. This is due to several TCP design principles that reflect the characteristi...
Giuseppe Anastasi, Emilio Ancillotti, Marco Conti,...
ISSAC
2009
Springer
144views Mathematics» more  ISSAC 2009»
16 years 25 days ago
H-LLL: using householder inside LLL
We describe a new LLL-type algorithm, H-LLL, that relies on Householder transformations to approximate the underlying Gram-Schmidt orthogonalizations. The latter computations are ...
Ivan Morel, Damien Stehlé, Gilles Villard