285 search results - page 31 / 57 » Performance and Functional Verification of Microprocessors |
129
Voted
VLSID
2000
IEEE
15 years 8 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
114
Voted
ISCA
1998
IEEE
15 years 8 months ago
1998
IEEE
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
120
Voted
IWANN
1997
Springer
15 years 7 months ago
1997
Springer
We present an implementation of Kohonen Self-Organizing Feature Maps for the Spert-II vector microprocessor system. The implementation supports arbitrary neural map topologies and ...
113
Voted
RTAS
2000
IEEE
15 years 7 months ago
2000
IEEE
Policing of incoming packets can produce very high load in worst-case situations on a receiving computer. In realtime systems, resources must be allocated for such worstcase situa...
98
Voted
ASPDAC
2008
ACM
15 years 5 months ago
2008
ACM
- Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off be...