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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 5 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
RTSS
2006
IEEE
15 years 5 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
SRDS
2006
IEEE
15 years 5 months ago
MOve: Design of An Application-Malleable Overlay
Peer-to-peer overlays allow distributed applications to work in a wide-area, scalable, and fault-tolerant manner. However, most structured and unstructured overlays present in lit...
Sébastien Monnet, Ramsés Morales, Ga...
ASPLOS
2006
ACM
15 years 5 months ago
Improving software security via runtime instruction-level taint checking
Current taint checking architectures monitor tainted data usage mainly with control transfer instructions. An alarm is raised once the program counter becomes tainted. However, su...
Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou
BIBE
2005
IEEE
15 years 5 months ago
Selecting Informative Genes from Microarray Dataset by Incorporating Gene Ontology
Selecting informative genes from microarray experiments is one of the most important data analysis steps for deciphering biological information imbedded in such experiments. Howev...
Xian Xu, Aidong Zhang
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