157 search results - page 18 / 32 » Performance area efficiency in chip multiprocessors with mic... |
95
Voted
VLSID
2002
IEEE
16 years 4 days ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
107
click to vote
DFT
2009
IEEE
15 years 6 months ago
2009
IEEE
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
111
Voted
TC
2010
14 years 10 months ago
2010
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
FPGA
2006
ACM
15 years 3 months ago
2006
ACM
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
DAC
2007
ACM
16 years 23 days ago
2007
ACM
Multicore has shown significant performance and power advantages over single cores in commercial systems with a 2-4 cores. Applying a corollary of Moore's Law for multicore, ...