1007 search results - page 111 / 202 » Performance based design of high-level language-directed com... |
DAC
2007
ACM
15 years 11 months ago
2007
ACM
We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works ha...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
DAC
2009
ACM
15 years 11 months ago
2009
ACM
Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...
CF
2004
ACM
15 years 3 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
IWCMC
2006
ACM
15 years 3 months ago
2006
ACM
This paper introduces project TITAN, which investigates an alternative construct of residential broadband access. The aim of the project is to increase the utilisation of deployed...