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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
IFIP
1993
Springer
15 years 1 months ago
Plant Engineering: Conceptual Modeling and Modular Design of a Computer Aided Environment
When designing a plant for continuous or semi-continuous processes, such as paper pulp or petrochemical production systems, engineers face very complex tasks, which are only in pa...
Cláudio Walter, José Palazzo M. de O...
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 2 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
JPDC
2000
141views more  JPDC 2000»
14 years 9 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
DAC
1994
ACM
15 years 1 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
Sudip Nag, Rob A. Rutenbar