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75
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DAC
2005
ACM
14 years 11 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
WETICE
2006
IEEE
15 years 3 months ago
A Model-Driven Framework for Managing the QoS of Collaborative P2P Service-Based Applications
1 Distributed and collaborative applications are rapidly converging towards the adoption of a computing paradigm based on service-oriented architectures, according to which an appl...
Michele Angelaccio, Andrea D'Ambrogio
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
15 years 2 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
80
Voted
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
15 years 4 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
IPPS
1998
IEEE
15 years 1 months ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...