Sciweavers

1007 search results - page 28 / 202
» Performance based design of high-level language-directed com...
Sort
View
DSN
2006
IEEE
15 years 3 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin
IDA
2009
Springer
15 years 4 months ago
Selecting Computer Architectures by Means of Control-Flow-Graph Mining
Abstract Deciding which computer architecture provides the best performance for a certain program is an important problem in hardware design and benchmarking. While previous approa...
Frank Eichinger, Klemens Böhm
CAL
2007
14 years 9 months ago
Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture
—Flash memory solid state disk (SSD) is gaining popularity and replacing hard disk drive (HDD) in mobile computing systems such as ultra mobile PCs (UMPCs) and notebook PCs becau...
Jinhyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong, Hongs...
PC
2007
161views Management» more  PC 2007»
14 years 9 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
DAC
2002
ACM
15 years 10 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...