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106
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IPPS
1999
IEEE
15 years 1 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 2 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
DSRT
2009
IEEE
15 years 28 days ago
An Approach for Parallel Interest Matching in Distributed Virtual Environments
—Interest management is essential for real-time large-scale distributed virtual environments (DVEs) which seeks to filter irrelevant messages on the network. Many existing inter...
Elvis S. Liu, Georgios K. Theodoropoulos
DAC
2003
ACM
15 years 2 months ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich
92
Voted
ICSEA
2007
IEEE
15 years 4 months ago
Sycophant: An API for Research in Context-Aware User Interfaces
Research in context-aware user interfaces aims to improve human-computer interaction by providing more effective, smarter and user-friendlier solutions for computer applications. ...
Anil Shankar, Juan C. Quiroz, Sergiu M. Dascalu, S...