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DAC
2008
ACM
14 years 11 months ago
Programmable logic circuits based on ambipolar CNFET
Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PL...
M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebic...
ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
15 years 2 months ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...
WOSP
2005
ACM
15 years 3 months ago
Modeling the performance of a NAT/firewall network service for the IXP2400
The evolution towards IP-aware access networks creates the possibility (and, indeed, the desirability) of additional network services, like firewalling or NAT, integrated into th...
Tom Verdickt, Wim Van de Meerssche, Koert Vlaeminc...
ERSA
2006
111views Hardware» more  ERSA 2006»
14 years 11 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
ICPPW
2002
IEEE
15 years 2 months ago
A Statistical Approach for the Analysis of the Relation Between Low-Level Performance Information, the Code, and the Environment
This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design o...
Nayda G. Santiago, Diane T. Rover, Domingo Rodr&ia...