1007 search results - page 41 / 202 » Performance based design of high-level language-directed com... |
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
63
Voted
NIXDORF
1992
15 years 1 months ago
1992
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
89
Voted
DAC
2010
ACM
15 years 1 months ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
ERSA
2004
14 years 11 months ago
2004
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
APCSAC
2000
IEEE
15 years 2 months ago
2000
IEEE
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...