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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 6 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
SIGMOD
2010
ACM
260views Database» more  SIGMOD 2010»
15 years 6 months ago
Towards proximity pattern mining in large graphs
Mining graph patterns in large networks is critical to a variety of applications such as malware detection and biological module discovery. However, frequent subgraphs are often i...
Arijit Khan, Xifeng Yan, Kun-Lung Wu
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
15 years 4 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
ATAL
2008
Springer
15 years 3 months ago
A statistical relational model for trust learning
We address the learning of trust based on past observations and context information. We argue that from the truster's point of view trust is best expressed as one of several ...
Achim Rettinger, Matthias Nickles, Volker Tresp
BCS
2008
15 years 2 months ago
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
Andreas Fidjeland, Wayne Luk, Stephen Muggleton
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