Sciweavers

121 search results - page 1 / 25
» Performance evaluation for system-on-chip architectures usin...
Sort
View
104
Voted
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 5 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
CODES
2009
IEEE
15 years 3 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
95
Voted
ARCS
2006
Springer
15 years 2 months ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...
95
Voted
EUROPAR
2008
Springer
15 years 19 days ago
DGSim: Comparing Grid Resource Management Architectures through Trace-Based Simulation
Abstract. Many advances in grid resource management are still required to realize the grid computing vision of the integration of a worldwide computing infrastructure for scientifi...
Alexandru Iosup, Omer Ozan Sonmez, Dick H. J. Epem...
82
Voted
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
15 years 2 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm