432 search results - page 85 / 87 » Performance evaluation of a new parallel preconditioner |
TC
2008
14 years 9 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
ALGORITHMICA
2002
14 years 9 months ago
2002
We consider the total weighted completion time scheduling problem for parallel identical machines and precedence constraints, P jprecj PwiCi. This important and broad class of pro...
186
click to vote
GLVLSI
2011
IEEE
14 years 1 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
IPSN
2007
Springer
15 years 4 months ago
2007
Springer
The development of high-level programming environments is essential if wireless sensor networks are to be accessible to nonexperts. In this paper, we present the Regiment system, ...