Sciweavers

5281 search results - page 111 / 1057
» Performance evaluation of software architectures
Sort
View
MOBICOM
2004
ACM
15 years 10 months ago
Performance evaluation of safety applications over DSRC vehicular ad hoc networks
In this paper we conduct a feasibility study of delay-critical safety applications over vehicular ad hoc networks based on the emerging dedicated short range communications (DSRC)...
Jijun Yin, Tamer A. ElBatt, Gavin Yeung, Bo Ryu, S...
ASPLOS
1991
ACM
15 years 8 months ago
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
LCN
1998
IEEE
15 years 9 months ago
High Performance Integrated Network Communications Architecture (INCA)
Current communication subsystem mechanisms within workstation and PC class computers are limiting network communications throughput to a small percentage of the present network da...
Klaus Schug, Anura P. Jayasumana, Prasanth Gopalak...
125
Voted
DATE
2008
IEEE
79views Hardware» more  DATE 2008»
15 years 11 months ago
System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture
Microcontrollers are the core part of automotive Electronic Control Units (ECUs). A significant investment of the ECU manufacturers and even their customers is linked to the speci...
Albrecht Mayer, Frank Hellwig
ASPLOS
2006
ACM
15 years 11 months ago
A performance counter architecture for computing accurate CPI components
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, J...