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193
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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
15 years 4 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
DAC
1994
ACM
15 years 10 months ago
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications
This paper presents a new method,based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expe...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
130
Voted
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
16 years 6 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 11 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
OPNETEC
2004
Springer
15 years 11 months ago
Performance of Optical Burst Switched WDM Ring Network with TTFR System
: In this paper, we propose an architecture of Optical Burst Switched WDM ring network. In our proposed OBS ring network, every node is equipped with one tunable transmitter and on...
Yutaka Arakawa, Naoaki Yamanaka, Iwao Sasase